This invention relates to test systems for complex LSI (Large Scale Integrated) circuit chips found in the state-of-the-art digital electronics systems. The provision of on chip logic module testing reduces the number of input and output terminations to the device and facilitates a complete test function of the module. The additional logic to be placed on such an LSI chip as a result of the internal test function is more easily accommodated than the requirements necessary to provide for external testing.
Problems relating to the testing of individual LSI chips or complete systems built from complex LSI technology developed because of the large number of test operands needed to provide good chip test coverage. If the test operands are applied by conventional methods through input pins and analyzed through the output of the chip, the test time becomes long and expensive. Also, the job of determining a valid set of complete test operands becomes an additional burden which is difficult and in fact becomes impractical for complex chips. Further, in the test environment where mechanical connection of electrical test equipment must be made to a large number of pin contacts for both input and output functions, is the unreliability and difficulty of duplicating good electrical contacts. Thus, a failed electrical contact will show as a defect in the testing procedure even where the chip can be good. Further, mechanical access to an LSI chip in a testing environment is difficult where test signals may be sampled from particular input and output pins of a chip in the system test environment. Thus, pin testing of LSI chips in the final system must be avoided.
Particularly difficult is the testing of logic on chips at the silicon wafer stage of manufacture. The cost of packaging requires testing on the wafer. Because the difficulty of obtaining good connections to over 100 pins on a wafer is so high, a test system reducing pin connections is particularly useful.
Known to applicant in the prior art is an article entitled "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams published in the Journal of Design Automation and Fault Tolerant Computing, Vol. 2, No. 2, May 1978, pp. 165-178. The paper shows a two-step design method for creating testable LSI chips. The first step is designed of sequential logic structures so that operation is not dependent on signal rise and fall times or on circuit transmission delays. The second step of the design process disclosed is to design all internal storage elements so that they can be operated as shift registers to facilitate testing and diagnostic functions. The point is that sequential logic can be transformed to combinational logic functions which are easier to test. While this paper gives an excellent background and references to state-of-the-art LSI chip testing, the paper does not show the use of independent shift registers and checksum logic systems as described in the present invention for designing LSI chip test systems.
U.S. Pat. Nos. 3,777,129 and 3,927,371 are also known to applicant. These patents show that the concept of having test related circuitry on an LSI chip is, by itself, old. These patents also show that LSI chips may be tested by using various signal input combinations which do not necessarily represent a specific checklist of exact functions to be performed. The present invention employs the concept of using signal input test combinations which do not necessarily represent the exact functions to be performed by the logic module. These patents are however distinguished from the present invention in that the combination of a logic, shift registers, checksum devices and control circuits provided in the present invention are not anticipated by the referenced patents.
Also known to applicant, is U.S. Pat. No. 3,723,868 which shows a printed circuit card tester which supplies a repetitive set of waveforms to the circuit under test as a stimulus to the tested function. Digital logic circuitry performs analysis of the output from the circuit under test which consists of counting output pulses during timed intervals in order to monitor edge transitions of signals. A fault is detected when distinct edge transitions of output signals of the circuit being tested do not occur between the selected time intervals. The relevance of this patent is with respect to the way the test signals are generated and the comparison of the output test signals with the logic function signals in the testing function. However, the present invention is not dependent upon edge transition time intervals or the same features to which the patent is directed.
Also known in the prior art, is U.S. Pat. No. 3,614,608 in which a test system provides a random number signal generator to simultaneously apply a plurality of signals in a random pattern to the plurality of input pens of a circuit under test and a perfectly operating reference circuit. Comparison circuitry is responsive to signals received from both circuits and provides another signal when the two outputs are not matched. This system requires a large number of test patterns to be generated in order to provide a reliable testing process. To increase the reliability to a desired high level, a very large number of random number test patterns must be applied. The patent discloses a system whereby reliability of the testing process is approached asymptotically with an increasing number of test generator input signals. The present invention discloses a system which is a complete and certain test of the circuit under test. Because of the test performed, the combination of the test system into the LSI chip becomes desirable and is not possible in the prior art patents referenced in which test circuitry is outside of the chip.